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ISL97692, ISL97693, ISL97694A
V BATT : 2.4 V~21 .8V
2.4V~5.5 V
4.7μF
VIN
L1
10 μH
D1
LX
4.7μF 4.7μF
100 pF 470 k
V OUT : 24 .5V , 6 x 20 mA
15 nF
12k
COMP
ISL97694A
OVP
2.2nF
23 .7k
ISET
53 k
291k
AGND
SDA/PWMI
SCL
EN
FPWM
FSW
PGND
CH1
CH2
CH3
CH4
CH5
CH6
143k
FIGURE 26. LED DRIVER OPERATION WITH INPUT VOLTAGE UP TO 26V
SMBus/I 2 C Communications
The ISL97694A is controlled by SMBus/I 2 C for PWM dimming, and
powers up in the shutdown state. The ISL97694A is enabled when
both the EN pin is high and the BL_CTL bit in register 0x01 is
programmed to 1.
Write Byte
The Write Byte protocol is only three bytes long. The first byte starts
with the slave address followed by the “command code,” which
translates to the “register index” being written. The third byte
contains the data byte that must be written into the register selected
by the “command code”. A shaded label is used on cycles during
which the slaved backlight controller “owns” or “drives” the Data
Slave Device Address
The slave address contains 7 MSB plus one LSB as R/W bit, but
these 8 bits are usually called Slave Address bytes. As shown in
Figure 27, the high nibble of the Slave Address byte is 0x5 or
b’0101’ to denote the “backlight controller class”. Bit 0 is always the
R/W bit, as specified by the SMBus/I 2 C protocol. If the device is in
the write mode where bit 0 is 0, the slave address byte is 0x5A or
b’01011010’. If the device is in the read mode where bit 0 is 1, the
slave address byte is 0x5B or b’01011011’.
MSB
line. All other cycles are driven by the “host master.”
0
1
0
1
1
0
1
R/W
Read Byte
As shown in Figure 30, the four byte long Read Byte protocol starts
out with the slave address followed by the “command code”, which
translates to the “register index.” Subsequently, the bus direction
turns around with the rebroadcast of the slave address with bit 0
indicating a read (“R”) cycle. The fourth byte contains the data
DEVICE IDENTIFIER
DEVICE ADDRESS
being returned by the backlight controller. That byte value in the
data byte reflects the value of the register being queried at the
“command code” index. Note the bus directions, which are
highlighted by the shaded label that is used on cycles during which
the slaved backlight controller “owns” or “drives” the Data line. All
other cycles are driven by the “host master.”
18
FIGURE 27. SLAVE ADDRESS BYTE DEFINITION
FN7839.4
December 20, 2012
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